What Are The Caller Saved Registers

Microprocessors and Microcontrollers

Kithsiri Samarasinghe , in Mod Component Families and Circuit Block Design, 2000

four.7.2 Register-Based Microprocessors

The internal annals bank of register-based microprocessors consists of both general purpose and special purpose registers. The programmer is complimentary to use full general purpose registers as appropriate to the specific example. For case, the Z80's A, B, C, DE, and HL registers all are general purpose ones. B and C may be used as a pair or individually, equally may the D and Eastward and H and Fifty registers.

In general when the number of registers in a microprocessor increases, the instruction set grows in size. Therefore, Z80, a register-based microprocessor, has a bigger instruction fix than a 6502 or M6800, which are accumulator based.

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Floating Point Operations

Joseph Yiu , in The Definitive Guide to ARM® CORTEX®-M3 and CORTEX®-M4 Processors (3rd Edition), 2014

13.2.4 Floating indicate register bank

The floating point register bank contains thirty-two 32-bit registers, which can exist organized as sixteen 64-chip double-word registers, as shown in Effigy 13.xiii.

S0 to S15 are caller saved registers. So if a function A calls a function B, function A must salve the contents of these registers (e.g., on the stack) before calling office B because these registers can exist changed by the function call (e.g., return outcome).

S16 to S31 are callee saved registers. So if a function A calls a function B, and function B needs to use more than than 16 registers for its calculations, it must salvage the contents of these registers (e.g., on the stack) first, and must restore these registers from the stack earlier returning to function A.

The initial values of these registers are undefined.

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Software Porting

Joseph Yiu , in The Definitive Guide to Arm® Cortex®-M0 and Cortex-M0+ Processors (Second Edition), 2015

22.iii.three Registers

The ARM7TDMI has a register bank with banked registers based on electric current functioning manner. In the Cortex-M0 or Cortex-M0+ processor, just the SP is banked. And in most simple applications without an Bone, only the Main Stack Pointer (MSP) is required. Figure 22.one shows the comparison of the register depository financial institution betwixt ARM7TDMI and Cortex-M0/M0+ processors.

In that location are some differences between the CPSR (Current Program Condition Register) in the ARM7TDMI and the xPSR in the Cortex-M processors. For example, the manner bits in CPSR are removed, replaced by IPSR, and interrupt masking chip I-bit is replaced by the PRIMASK register, which is separated from the xPSR.

Despite the differences betwixt the register banks, the developer's model or R0 to R15 remains the same. Every bit a issue, most Thumb^® instruction codes on ARM7TDMI can exist reused on Cortex-M processors, simplifying software porting.

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The Floating-Signal Unit of measurement (FPU) in the Cortex-M33 processor

Joseph Yiu , in Definitive Guide to Arm® Cortex®-M23 and Cortex-M33 Processors, 2021

14.ii.five Floating-bespeak register bank

The floating-betoken register bank contains thirty-two 32-bit registers, which tin be viewed as xvi 64-bit double word registers for double precision floating-point processing ( Fig. 14.13).

S0–S15 are caller-saved registers: If a function A calls a role B, role A must salvage the contents of these registers ( e.k., on the stack) earlier calling function B because these registers can exist inverse by the function call ( e.g., returning a result).

S16–S31 are callee-saved registers: If a function A calls a function B and function B needs to use more than xvi registers for its calculations, it must, start, save the contents of these registers ( due east.thou., on the stack) and and then restore these registers from the stack before returning to part A.

The initial values of these registers are undefined.

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Technical Overview

Joseph Yiu , in The Definitive Guide to Arm® Cortex®-M0 and Cortex-M0+ Processors (2d Edition), 2015

two.ii Block Diagrams

A simplified block diagram of the Cortex^®-M0 processor is shown in Effigy 2.2.

The processor core contains the register banks, ALU, data path, and control logic. It is a three-phase pipeline blueprint with fetch stage, decode phase, and execution stage. The register banking concern has sixteen 32-bit registers. A few of the registers in the register bank have special usages (e.grand., PC). The rest are available for general data processing.

The NVIC accepts upwardly to 32 interrupt request signals and a NMI input. It contains the functionality required for comparing priority between interrupt requests and electric current priority level so that nested interrupts can be handled automatically. If an interrupt is accepted, the NVIC communicates with the processor and then that the processor tin execute the right interrupt handler.

The WIC is an optional unit of measurement. In depression-ability applications, the microcontroller tin enter standby state with most parts of the processor powered downwardly. Under this situation, the WIC can perform the function of interrupt masking while the NVIC and the processor core are inactive. When an interrupt request is detected, the WIC informs the ability direction to ability upwardly the system so that the NVIC and the processor core can then handle the rest of the interrupt processing.

The debug subsystem contains various functional blocks to handle debug control, plan breakpoints, and data watchpoints. When a debug consequence occurs, it tin put the processor cadre in a halted land and so that embedded developers tin examine the status of the processor at that bespeak.

The internal bus system, data path in the processor core, and the AHB-Lite bus interface are all 32-bit broad. AHB-Lite is an on-chip double-decker protocol used in many ARM^® processors. This omnibus protocol is part of the AMBA^® (Advanced Microcontroller Coach Architecture) specification, which is a bus compages adult past ARM and widely used in the IC design industry.

The JTAG or Series Wire interface units provide access to the bus organization and debugging functionalities. The JTAG protocol is a popular 4-pin (5-pin if including a reset signal) communication protocol normally used for IC and PCB testing. The Serial Wire protocol is a newer advice protocol that simply requires two wires, only information technology tin can handle the aforementioned debug functionalities as JTAG. As illustrated in the cake diagrams (Figures 2.two and ii.iii), the debug interface module is separated from the processor blueprint. This is required in the CoreSight™ Debug Compages where multiple processors tin share the same debug connections. There are a number of additional signals for multiprocessor debug back up not shown in the diagrams.

The Cortex-M0+ processor is very similar (as shown in Figure 2.3) to Cortex-M0 processor. The simply addition is the adding of the optional MPU, single bicycle I/O interface omnibus and the interface for the MTB. The processor cadre internal pattern is also inverse to a two-stage pipeline arrangement.

The MPU is a programmable device used to ascertain access permission of the retentivity map. In some of the applications where an OS is used, awarding tasks can be executed with an unprivileged execution level with restrict retention access defined by the MPU, which is programmed by the Bone.

The single cycle I/O interface provides another autobus interface with faster admission compared to the AHB-Lite system bus (pipelined functioning). The MTB is used to provide instruction trace.

In both Cortex-M0 and Cortex-M0+ processors, a number of components in the processors are optional. For case, the debug support, MPU and the WIC are all optional. Another components like the NVIC are configurable: allowing chip designers to define the features bachelor, for example, the number of interrupt requests (IRQ).

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Compages

Joseph Yiu , in Definitive Guide to Arm® Cortex®-M23 and Cortex-M33 Processors, 2021

4.2.2.2 Registers in the register bank

Like to other Arm processors, there are a number of registers in the processor core for information processing and command. To perform an operation on data in the memory, the Arm processor must first load the data in a register, perform the performance in the processor and so, optionally, write back the consequence to the memory. This is commonly called "load-store compages". Registers are also used to agree address values to handle data transfers.

By having a sufficient number of registers in the register depository financial institution, C compilers can generate lawmaking to efficiently handle various operations. The register depository financial institution in Cortex-M processors has 16 registers: R0–R15 (see Fig. 4.6). Some of these registers take special usage as detailed beneath:

•: R13—Stack pointer (SP). It is used for accessing the stack memory (due east.g., stack Button or POP operations). Physically there can be ii or four stack pointers—the Secure stack pointers are available only when the TrustZone security extension is implemented. In that location is more information about the selection of stack pointers in Section four.iii.iv.
•: R14—Link register (LR). This annals is updated automatically to hold the return accost when calling a function or subroutine. At the cease of the function/subroutine, the value from LR is transferred into the programme counter (PC) in order to resume its operation. In the case of nested function calls (i.east., a function call is made within a function which was chosen past another code), the value in LR must outset be saved (e.g., using the stack Button operation to save the value into the stack memory) before the second level of function phone call is made. If information technology is not, the value in LR would be lost and would not be able to return to the original plan. LR is as well used to concur a special value called EXC_RETURN (Exception Return) during exception/interrupt handling. At the end of the interrupt service routine, the EXC_RETURN value is transferred into the PC to trigger the exception return. Further information on this is covered in Chapter 8, Sections 8.4.5 and 8.10.
•: R15—Program Counter (PC). The main advantage of having the PC in the register bank is that information technology makes accessing constant data in the program code easier (due east.thousand., Obtaining a constant using a data read educational activity with the "PC related addressing mode", for accessing a branch commencement in a table co-operative operation). It is too possible to read/write to the PC. When reading this register, the functioning returns a value which is the current instruction address (an even number), plus an offset of 4 (this is due to the pipeline nature of the processor and compatibility requirements with legacy processors, e.thou., the Arm7TDMI). Writing to this register causes a co-operative operation. However, it is recommended that normal branch instructions should be used for general branch operations.

The residuum of the registers (R0–R12) are general purpose. R0–R7 are also known as low registers. Because of the limited infinite available in a 16-flake instruction, many 16-fleck Thumb instructions can only access depression registers. The high registers (R8–R12) tin be used with 32-bit instructions, and a few 16-flake instructions similar MOV (move).

The initial values of R0–R12 tin be unpredictable at startup. The hardware startup sequence automatically initializes the value of the Secure Principal Stack Pointer (MSP_S) if the TrustZone security extension is implemented, or Non-secure Main Stack Pointer (MSP_NS) if it is non. The hardware startup sequence also initializes the program counter (R15/PC).

Further information on these registers is shown in Table four.one.

Tabular array 4.1. Read and write behaviors of registers R0–R15.

Registers	Initial value	Read/Write behaviors
R0–R12	Unknown	32-fleck, Read/Write allowed.
R13	MSP_S/MSP_NS is initialized by the hardware startup sequence	32-bit, but the lowest 2 bits are always 0 (stack pointer is always give-and-take aligned). Read/Write allowed and write-values to lowest two $.25 are ignored.
R14	Reset to 0xFFFFFFFF for Cortex-M33 (and other processors with the Mainline extension). Unknown for Cortex-M23 (Baseline)	32-scrap, Read/Write allowed. The value in R14 is also updated automatically when the processor has called a role or when it starts serving an interrupt/exception service. This allows the software catamenia to return to the caller or to the interrupted programme.
R15	PC is initialized past a hardware startup sequence	Fleck 0 is always 0, but when writing to the PC with indirect-co-operative instructions, bit 0 of the written value has a special meaning. Although it is possible to trigger a branch by writing to the PC (e.g., using a move instruction), it is, nonetheless, recommended to utilize co-operative instructions for normal branch operations.

In programming, registers R0–R15 can exist accessed using various names in either upper or lower case: R0–R15 or r0–r15. For R13–R15, it can also be accessed every bit

•: R13: SP or sp (current selected Stack Arrow)
•: R14: LR or lr (Link Annals)
•: R15: PC or pc (Program Counter)

As illustrated in Fig. iv.vi, the SP is banked between Secure and Not-secure states. When accessing the stack pointer with MSR/MRS instructions, it is possible to specify which stack pointer should be used:

•: MSP—Primary Stack Pointer of the current security state (could exist MSP_S or MSP_NS)
•: PSP—Process Stack Pointer of the electric current security country (could be PSP_S or PSP_NS)
•: MSP_NS—This enables Secure software to access the Not-secure Master Stack Pointer
•: PSP_NS—This enables Secure software to access the Non-secure Procedure Stack Pointer

In Arm documentation (eastward.g., Armv8-M Architecture Reference Manual), the stack pointers are also labeled every bit SP_main (Main Stack Pointer) and SP_process (Procedure Stack Arrow).

More than information about stack pointer operations is covered in Department 4.3.4.

R0–R15 tin besides exist accessed (read and write) by using debug software (running on a debug host such as a PC) when the processor is in the debug country (i.east., halted).

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Exception Programming

Joseph Yiu , in The Definitive Guide to the ARM Cortex-M3 (2nd Edition), 2010

eleven.six SVC Instance: Employ for Text Message Output Functions

Previously we adult various subroutines for output functions. Sometimes it is not good enough to employ BL to call the subroutines—for example, when the software lawmaking is running in nonprivileged access level and the text output I/O need privileged accesses. In these cases, we might want to utilise SVC to act every bit an entry point for the output functions. For example, a user program tin use SVC with different parameters to access different services:

LDR R0,=HELLO_TXT

SVC #0 ; Brandish string pointed to by R0

MOV R0,#'A'

SVC #one ; Display character in R0

LDR R0,=0xC123456

SVC #two ; Display hexadecimal value in R0

MOV R0,#1234

SVC #3 ; Brandish decimal value in R0

To utilise SVC, we might need to set up up the SVC handler if the vector table is relocated to SRAM. We tin modify the function that we have created to handle the interrupt (SetupIrqHandler part in previous section). The only difference is that this function takes an exception type as input (SVC is exception type xi). In add-on, this time nosotros have farther optimized the lawmaking to employ the 32-bit Pollex instruction features:

SetupExcpHandler ; Setup vector in relocated vector table in SRAM

;Input R0 = Exception number

; R1 = Exception handler

Push {R0, R2, LR}

LDR R2,=NVIC_VECTTBL ; Become vector table offset

LDR R2,[R2]

STR.W R1,[R2, R0, LSL #ii] ; shop vector handler in [R2+R0<<2]

Popular {R0, R2, PC} ; Return

For svc_handler, the SVC calling number can be extracted as in the previous example, and the parameter passed to the SVC can exist accessed by reading from the stack. In addition, the decision branches to reach various functions are added:

svc_handler

TST LR, #0x4 ; Test EXC_RETURN number in LR bit two

ITTEE EQ ; if aught (equal) and then

MRSEQ R1, MSP ; Main Stack was used, put MSP in R1

MRSNE R1, PSP ; else, Process Stack was used, put PSP

; in R1

LDR R0,[R1,#0] ; Get stacked R0 from stack

LDR R1,[R1,#24] ; Get stacked PC from stack

LDRB R1,[R1,#−two] ; Get the immediate data from the

; instruction

; At present the immediate data is in R1, input parameter is in R0

PUSH {LR} ; Store LR to stack

CBNZ R1,svc_handler_1

BL Puts ; Branch to Puts

B svc_handler_end

svc_handler_1

CMP R1,#1

BNE svc_handler_2

BL Putc ; Branch to Putc

B svc_handler_end

svc_handler_2

CMP R1,#2

BNE svc_handler_3

BL PutHex ; Branch to PutHex

B svc_handler_end

svc_handler_3

CMP R1,#iii

BNE svc_handler_4

BL PutDec ; Branch to PutDec

B svc_handler_end

svc_handler_4

B fault ; input non known

...

svc_handler_end

POP {PC} ; Render

The svc_handler lawmaking should be put close together with the outputting functions so that we can ensure that they are within the allowed branch range.

Observe that instead of the current contents of the register banking company, the stacked register contents are used for parameter passing. This is considering if a college-priority interrupt takes place when the SVC is executed, the SVC starts immediately after other interrupt handlers (tail chaining), and the contents of R0–R3 and R12 might be changed by the executed interrupt handler. This is acquired by the characteristic that unstacking is not carried out if there is tail chaining of interrupts. For case:

1.: A parameter is put in R0.
2.: SVC is executed at the same fourth dimension every bit a higher-priority interrupt takes place.
3.: Stacking is carried out, and R0–R3, R12, LR, PC, and xPSR are saved to the stack.
4.: The interrupt handler is executed. R0–R3 and R12 tin be changed by the handler. This is acceptable considering these registers will be restored past hardware unstacking.
5.: The SVC handler tail bondage the interrupt handler. When SVC is entered, the contents in R0–R3 and R12 can exist unlike from the value when SVC is chosen. Withal, the correct parameter is stored in the stack and can be accessed by the SVC handler.

Make the Almost of the Addressing Modes

From the code examples of the SetupIrqHandler and SetupExcpHandler routines, we observe that the code can be shortened a lot if we use the addressing fashion feature in the Cortex-M3. In SetupIrqHandler, the destination address of the IRQ vector is calculated, and then, the store is carried out:

SetupIrqHandler /* R0 = IRQ number, R1 = handler accost */

PUSH {R0, R2, LR}

LDR R2,=NVIC_VECTTBL ; Get vector table kickoff ; Stride ane

LDR R2,[R2] ; Stride 2

ADD R0, #16 ; Exception number = IRQ number + 16 ; Pace 3

LSL R0, R0, #ii ; Times iv (each vector is four bytes); Step iv

Add R2, R0 ; Find vector accost ; Step v

STR R1,[R2] ; store vector handler ; Stride half-dozen

Pop {R0, R2, PC} ; Return

In SetupExcpHandler, the operation Steps four–6 are reduced to just 1 step:

SetupExcpHandler /* R0 = exception number, R1 = handler address */

Button {R0, R2, LR}

LDR R2,=NVIC_VECTTBL ; Become vector table offset

LDR R2,[R2]

STR.W R1,[R2, R0, LSL #2] ; shop vector handler in

; [R2+R0<<ii]

Pop {R0, R2, PC} ; Return

In general, nosotros tin can reduce the number of instructions required if the information address is like one of these:

•: Rn + (ii^Due north) × Rm
•: Rn +/− immediate_offset

For the SetupIrqHandler routine, the shortest code we can get is this:

SetupIrqHandler

Push button {R0, R2, LR}

LDR R2,=NVIC_VECTTBL ; Go vector tabular array offset ; Pace one

LDR R2,[R2] ; Step 2

Add R2, #(16*4) ; Become IRQ vector start ; Step 3

STR.W R1,[R2, R0, LSL #2]; Store vector handler ; Step 4

POP {R0, R2, PC} ; Render

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Exceptions and interrupts—Architecture overview

Joseph Yiu , in Definitive Guide to Arm® Cortex®-M23 and Cortex-M33 Processors, 2021

8.nine.2 Interface of C functions

Based on the AAPCS specification [3], a C function can modify registers R0–R3, R12, LR(R14), and the PSR within C function boundaries. If the floating-bespeak unit of measurement is present and enabled, the registers in S0–S15 and the FPSCR (Floating Point Status and Command Annals) tin also be modified by the C role. The contents on the other registers can also be modified within the C functions, but the contents of these other registers volition demand to exist saved to the stack before being modified. And, before leaving the C function these registers must be restored to their original values.

Because of the aforementioned C office requirements, registers in the register bank and in the floating-point unit register bank are divided into:

-: Caller saved registers––R0–R3, R12, LR (also S0–S15 and FPSCR if the FPU is present). If the information in these registers needs to be used after a C part call, the caller needs to salvage it earlier calling a C part.
-: Callee saved registers––R4-R11 (also S16-S31 if the FPU is nowadays). If the C function needs to alter any of these registers, the C role must first push the affected registers to the stack and then restore them earlier returning to caller code.

In addition to caller and callee saved annals arrangement, the AAPCS specification also specifies how parameters and results can be passed between caller and callee. In a simple scenario, registers R0–R3 can be used as input parameters for C functions. Additionally, annals R0 and, optionally, register R1 can be used for returning the results of a function (register R1 is needed when the return value is 64-bit). Fig. 8.16 shows the grouping of callee-saved registers and the usage of several caller saved registers for parameters and result passing.

Another requirement of the AAPCS is that the value of the stack pointer must exist aligned to double give-and-take boundaries at a role interface. The processor's exception handling hardware handles this automatically.

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Architecture

Joseph Yiu , in The Definitive Guide to Arm® Cortex®-M0 and Cortex-M0+ Processors (Second Edition), 2015

Admission of Registers and Special Registers

In C/C++ programming or whatsoever other high level languages, the registers in the register bank (R0–R12) can exist utilized by the compiler automatically. In most cases, you exercise non need to worry nearly which registers being used, unless y'all are interfacing assembly code and C/C++ code (such mixed language development will be encompass in Affiliate 21).

The other special registers need to be accessed using some special instructions (MRS and MSR). The CMSIS-CORE provides a number of APIs for such usages. However, please note that some of these special registers cannot be accessed or changed by software (Table 4.ane).

Table 4.1. Access limitations to special registers

	Privileged	Unprivileged
APSR	R/W	R/W
EPSR	No admission (T bit read every bit zero)	No access (T flake read equally nada)
IPSR	Read but	Read only
PRIMASK	R/Due west	Read only
CONTROL	R/Westward	Read only

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PIC Programming

Martin Bates , in Interfacing Moving-picture show Microcontrollers (Second Edition), 2014

2.iv.two.1 TRIS

This was an instruction originally provided to brand port initialisation simpler (see programme LED1). It selects register bank ane so that the TRIS data direction registers (TRISA, TRISB, etc.) tin be loaded with a information direction code (0=output). The manufacturer no longer recommends apply of this teaching, although information technology is still supported by the electric current assembler versions and is useful when learning with very simple programs. The assembler directive BANKSEL should be used in virtually programs, because it gives access to all the registers in banks ane, 2 and 3. The other option is to change the bank select $.25 RP0 and RP1 explicitly in the Condition register directly, using BSF and BCF.

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