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How To Add Two Data Registers In Motorola

Written By Thursday, 2 June 2022 Add Comment Edit
Motorola 68000
Designer Motorola
$.25 sixteen/32-bit
Introduced 1979
Design CISC
Endianness Big
Registers
General purpose viii �- 32-bit + 7 address registers also usable for most operations + stack pointer

The Motorola 68000 (also called the Motorola 68K) is a xvi/32-fleck [1] CISC microprocessor core designed and marketed by Motorola Semiconductor Products Sector (now Freescale Semiconductor). Introduced in 1979 with HMOS technology as the first member of the successful 32-bit m68k family of microprocessors, it is generally software forrard compatible with the rest of the line despite being limited to a sixteen-bit wide external bus. After 30 years in production, the 68000 architecture is still in employ.

Pre-release XC68000 scrap manufactured in 1979.

Contents

  • ane History
    • 1.1 Second-sourcing
    • 1.ii CMOS versions
    • 1.3 Equally a microcontroller cadre
  • 2 Applications
  • 3 Compages
    • three.i Address bus
    • 3.2 Internal registers
    • 3.3 Status annals
    • three.4 Instruction set
    • three.5 Privilege levels
    • 3.6 Interrupts
  • four Instruction set details
  • 5 68EC000
  • 6 See as well
  • 7 Notes
  • 8 References
  • 9 External links

History

Motorola MC68000 (CLCC package)

Motorola MC68000 (PLCC package)

The 68000 grew out of the MACSS (Motorola Avant-garde Estimator System on Silicon) project, begun in 1976 to develop an entirely new compages without backward compatibility. It would be a college-power sibling complementing the existing 8-chip 6800 line rather than a uniform successor. In the end, the 68000 did retain a bus protocol compatibility mode for existing 6800 peripheral devices, and a version with an viii-chip data motorcoach was produced. However, the designers mainly focused on the time to come, or forrard compatibility, which gave the M68K platform a caput kickoff against after 32-fleck instruction set architectures. For instance, the CPU registers are 32 $.25 broad, though few self-contained structures in the processor itself operate on 32 bits at a time. The MACSS squad drew heavily on the influence of minicomputer processor design, such as the PDP-eleven and VAX systems, which were similarly microcoded.

In the mid 1970s, the 8-bit microprocessor manufacturers raced to innovate the xvi-bit generation. National Semiconductor had been kickoff with its IMP-16 and PACE processors in 1973-1975, but these had issues with speed. The Intel 8086 in 1977 rapidly gained popularity. The decision to leapfrog the competition and innovate a hybrid 16/32-bit design was necessary, and Motorola turned it into a coherent mission. Arriving belatedly to the 16-chip arena afforded the new processor more transistors (roughly twoscore 000 active versus 20 000 active in the 8086), 32-chip macroinstructions, and acclaimed general ease of use.

The original MC68000 was made using an HMOS process with a 3.5-micron feature size. Formally introduced in September 1979, [two] Initial samples were released in February 1980, with production chips available over the counter in November. [3] Initial speed grades were 4, 6, and viii MHz. 10 MHz chips became available during 1981[ citation needed ], and 12.5 MHz chips by June 1982. [4] The 16.67 MHz "12F" version of the MC68000, the fastest version of the original HMOS scrap, was not produced until the late 1980s. Tom Gunter, retired Corporate Vice President at Motorola, is known as the "Father of the 68000."

The 68000 became the dominant CPU for Unix based workstations including Sun workstations and Apollo/Domain workstations, and besides was used for mass-market place computers such as the Apple Lisa, Macintosh, Amiga, and Atari ST. The 68000 was used in Microsoft Xenix systems besides as a epitome Netware Unix based Server (after the MC6800 series was non found to be powerful enough and before the move to Intel 8X086 processors). The 68000 was used in the first generation of desktop laser printers including the original Apple Inc. LaserWriter and the HP LaserJet. In 1982, the 68000 received an update to its ISA allowing it to support virtual retention and to conform to the Popek and Goldberg virtualization requirements. The updated chip was called the 68010. A farther extended version which exposed 31 bits of the address bus was likewise produced, in small quantities, every bit the 68012.

To support lower-cost systems and command applications with smaller memory sizes, Motorola introduced the 8-bit compatible MC68008, likewise in 1982. This was a 68000 with an 8-bit information charabanc and a smaller (20 bit) accost bus. After 1982, Motorola devoted more than attending to the 68020 and 88000 projects.

Second-sourcing

Thomson TS68000

Several other companies were second-source manufacturers of the HMOS 68000. These included Hitachi (HD68000), who shrank the feature size to 2.vii-microns for their 12.5 MHz version, [5] Mostek (MK68000), Rockwell (R68000), Signetics (SCN68000), Thomson/SGS-Thomson (originally EF68000 and later TS68000), and Toshiba (TMP68000). Toshiba was also a 2d-source maker of the CMOS 68HC000 (TMP68HC000).

CMOS versions

The 68HC000, the first CMOS version of the 68000, was designed by Hitachi and jointly introduced in 1985. [6] Motorola'south version was called the MC68HC000, while Hitachi'southward was the HD68HC000. The 68HC000 was somewhen offered at speeds of eight-20 MHz. Except for using CMOS circuitry, it behaved identically to the HMOS MC68000, but the change to CMOS profoundly reduced its power consumption. The original HMOS MC68000 consumed effectually 1.35 watts at an ambient temperature of 25 °C, regardless of clock speed, while the MC68HC000 consumed but 0.13 watts at 8 MHz and 0.38 watts at 20 MHz. (Dissimilar CMOS circuits, HMOS still draws power when idle, so ability consumption varies little with clock charge per unit.) Apple selected the 68HC000 for utilise in the Macintosh Portable.

Motorola replaced the MC68008 with the MC68HC001 in 1990. [7] This chip resembled the 68HC000 in most respects, but its data autobus could operate in either 16-bit or 8-bit mode, depending on the value of an input pin at reset. Thus, similar the 68008, it could exist used in systems with cheaper viii-fleck memories.

The later evolution of the 68000 focused on more than modern embedded control applications and on-chip peripherals. The 68EC000 chip and SCM68000 cadre expanded the address bus to 32 bits, removed the M6800 peripheral bus, and excluded the Move from SR instruction from user fashion programs. [viii] In 1996, Motorola updated the standalone core with fully static circuitry drawing only two µW in low-power mode, calling it the MC68SEC000. [9]

Motorola ceased production of the HMOS MC68000 and MC68008 in 1996, [10] but its spin-off company, Freescale Semiconductor, is notwithstanding producing the MC68HC000, MC68HC001, MC68EC000, and MC68SEC000, equally well as the MC68302 and MC68306 microcontrollers and later on versions of the DragonBall family. The 68000's architectural descendants, the 680x0, CPU32, and Coldfire families, are also still in production.

Every bit a microcontroller core

Later beingness succeeded by "true" 32-bit microprocessors, the 68000 was used as the core of many microcontrollers. In 1989, Motorola introduced the MC68302 communications processor. [11]

Applications

Two Hitachi 68HC000 CPUs being used on an arcade game PCB

At its introduction, the 68000 was start used in high-priced systems, including multiuser microcomputers like the WICAT 150 [5], early on Alpha Microsystems computers, Sage II / IV, Tandy TRS-fourscore Model 16, and Fortune 32:sixteen; single-user workstations such as Hewlett-Packard's HP 9000 Series 200 systems, the get-go Apollo/Domain systems, Sun Microsystems' Lord's day-ane, and the Corvus Concept; and graphics terminals like Digital Equipment Corporation's VAXstation 100 and Silicon Graphics' IRIS thou and 1200. Unix systems apace moved to the more capable afterward generations of the 68k line, which remained popular in that market throughout the 1980s.

By the mid-1980s, falling production toll made the 68000 viable for employ in personal and home computers, starting with the Apple Lisa and Macintosh, and followed by the Commodore Amiga, Atari ST, and Sharp X68000. The 68008, on the other mitt, was simply used in a few domicile figurer systems. The Sinclair QL (though the QL was a sis motorcar to the ICL Ane Per Desk, which too used a 68008) was the near commercially important. Helix Systems (in Missouri, United States) designed an extension to the SWTPC SS-50 bus, the SS-64, and produced systems congenital around the 68008 processor.

While the rapid pace of reckoner advancement speedily rendered the 68000 obsolete equally desktop/workstation CPU, the processor found substantial use in embedded applications. Past the early 1980s, quantities of 68000 CPUs could be purchased for less than $30 USD per office. Video game manufacturers used the 68000 as the courage of many arcade games and domicile game consoles: Atari's Food Fight, from 1982, was one of the offset 68000-based arcade games. Others included Sega'south Arrangement sixteen, Capcom's CP Organization and CPS-2, and SNK's Neo Geo. By the late 1980s, the 68000 was inexpensive enough to power home game consoles, such as Sega's Mega Drive (Genesis) console. The 1993 multi-processor Atari Jaguar console used a 68000 as a back up fleck, although some developers used it as the primary processor due to familiarity. The 1994 multi-processor Sega Saturn panel used the 68000 every bit a audio chip.

The 68000 as well saw great success every bit an embedded controller. As early as 1981, laser printers such as the Imagen Imprint-10 were controlled by external boards equipped with the 68000. The beginning HP LaserJet—introduced in 1984—came with a built-in 8 MHz 68000. Other printer manufacturers adopted the 68000, including Apple tree with its introduction of the LaserWriter in 1985, the beginning PostScript laser printer. The 68000 continued to be widely used in printers throughout the residuum of the 1980s, persisting well into the 1990s in low-terminate printers.

The 68000 also saw success in the field of industrial control systems. Amid the systems which benefited from having a 68000 or derivative as their microprocessor were families of Programmable Logic Controllers (PLCs) manufactured by Allen-Bradley, Texas Instruments and subsequently, following the conquering of that division of TI, past Siemens. Users of such systems do not accept product obsolescence at the same rate equally domestic users and information technology is entirely probable that despite having been installed over 20 years agone, many 68000-based controllers will go on in reliable service well into the 21st century.

The 683XX microcontrollers, based on the 68000-compages, are used in networking and telecom equipment, television ready-peak boxes, laboratory and medical instruments, and even handheld calculators. The MC68302 and its derivatives take been used in many telecom products from Cisco, 3com, Ascend, Marconi, Cyclades and others. Past models of the Palm PDAs and the Handspring Visor used the DragonBall, a derivative of the 68000. AlphaSmart uses the DragonBall family in later versions of its portable word processors. Texas Instruments uses the 68000 in its loftier-end graphing calculators, the TI-89 and TI-92 series and Voyage 200. Early on versions of these used a specialized microcontroller with a static 68EC000 core; afterwards versions use a standard MC68SEC000 processor.

A modified version of the 68000 formed the basis of the IBM XT/370 Hardware emulator of a System 370 processor.

Architecture

Accost bus

The 68000 has a 24-bit external address charabanc and two byte-select signals "replaced" A0. These 24 lines could therefore reach 16 MB of concrete retentiveness with byte resolution. Address storage and computation used 32 bits, however, with the loftier-order byte ignored due to the physical lack of pins. This allowed it to run software written for a flat 32-bit address space. Motorola's intent[ citation needed ] with the internal 32-bit accost infinite was forward compatibility, making information technology viable to write 68000 software that would take full advantage of later 32-chip implementations of the 68000 instruction ready. [12]

However, this did not prevent programmers from writing forward incompatible software. "24-bit" software that discarded the upper address byte, or used it for purposes other than addressing, could fail on 32-bit 68K implementations. For case, early (pre-vii.0) versions of Apple's Mac Bone used the loftier byte of memory-block master pointers to hold flags such as locked and purgeable. Later versions of the OS moved the flags to a nearby location, and Apple began shipping computers which had "32-flake clean" ROMs beginning with the release of the 1989 Mac IIci.

Internal registers

The CPU has 8 32-bit general-purpose data registers (D0-D7), and 8 accost registers (A0-A7). The last accost register is the stack pointer, and assemblers would have the label SP equally equivalent to A7. This was a practiced number of registers in many ways. It was modest plenty to permit the 68000 to answer apace to interrupts (because all 8 data registers D0 - D7 and 7 accost registers A0 - A6 have to exist saved, 15 registers in total), and nonetheless big enough to make most calculations fast. Annotation that an exception routine in supervisor way could also accept saved the user stack pointer A7, which would make it eight address registers.

Having two types of registers was mildly abrasive at times, but non difficult to use in do. Reportedly, information technology immune the CPU designers to achieve a college caste of parallelism, by using an auxiliary execution unit for the address registers.

Integer representation in the 68000 family is big-endian.

Status register

The 68000 comparison, arithmetic and logic operations set up chip flags in a condition register to record their results for use by later conditional jumps. The bit flags were "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, considering it was separated from the carry flag. This permitted the extra bit from arithmetic, logic, and shift operations to be separated from the comport for menses-of-control and linkage.

Instruction gear up

The designers attempted to brand the associates language orthogonal. That is, instructions were divided into operations and address modes, and near all address modes were available for almost all instructions. There were 56 instructions and a minimum teaching size of 16 bits. Many instructions and addressing modes were longer to include additional accost or mode $.25.

Privilege levels

The CPU, and later the whole family, implemented two levels of privilege. User style gave access to everything except the interrupt level control. Supervisor privilege gave access to everything. An interrupt always became supervisory. The supervisor chip was stored in the status annals, and was visible to user programs.

An reward of this system was that the supervisor level has a separate stack pointer. This permitted a multitasking system to employ very pocket-sized stacks for tasks, considering the designers did not have to allocate the memory required to hold the stack frames of a maximum stack-up of interrupts.

Interrupts

The CPU recognized vii interrupt levels. Levels 1 through 7 were strictly prioritized. That is, a higher-numbered interrupt could always interrupt a lower-numbered interrupt. In the status annals, a privileged educational activity immune ane to gear up the current minimum interrupt level, blocking lower or equal priority interrupts. For case, if the interrupt level in the status register is set to 3, college levels from 4 to 7 could have acquired an exception. Level 7 was a level triggered Non-maskable interrupt (NMI). Level ane could be interrupted by any higher level. Level 0 ways no interrupt. The level was stored in the status register, and was visible to user-level programs.

Hardware interrupts are signalled to the CPU using iii inputs that encode the highest pending interrupt priority. A separate Encoder is usually required to encode the interrupts, though for systems that do not require more than than three hardware interrupts it is possible to connect the interrupt signals straight to the encoded inputs at the cost of additional software complexity. The interrupt controller can exist as elementary as a 74LS148 priority encoder, or may be office of a VLSI peripheral bit such as the MC68901 Multi-Function Peripheral (used in Atari TT030), which also provided a UART, timer, and parallel I/O.

The "exception table" (interrupt vector tabular array interrupt vector addresses) was fixed at addresses 0 through 1023, permitting 256 32-scrap vectors. The offset vector (RESET) consisted of ii Vectors, namely the starting stack accost, and the second was the starting lawmaking address. Vectors 3 through xv were used to report various errors: bus fault, address fault, illegal instruction, nix division, CHK & CHK2 vector, privilege violation (to block privilege escalation), and some reserved vectors that became line 1010 emulator, line 1111 emulator, and hardware breakpoint. Vector 24 started the real interrupts: spurious interrupt (no hardware acknowledgement), and level i through level 7 autovectors, and then the 16 TRAP vectors, then some more reserved vectors, then the user defined vectors.

Since at a minimum the starting code accost vector must always be valid on reset, systems commonly included some nonvolatile retentivity (e.g. ROM) starting at address zero to contain the vectors and bootstrap code. However, for a full general purpose system it is desirable for the operating arrangement to be able to alter the vectors at runtime. This was often achieved by either pointing the vectors in ROM to a jump table in RAM, or through utilise of depository financial institution switching to permit the ROM to be replaced by RAM at runtime.

The 68000 did not run across the Popek and Goldberg virtualization requirements for full processor virtualization because it has a single unprivileged didactics "MOVE from SR", which allowed user-mode software read-only access to a small corporeality of privileged state.

The 68000 was also unable to hands support virtual retentiveness, which requires the ability to trap and recover from a failed retention admission. The 68000 does provide a bus error exception which can exist used to trap, but information technology does not save enough processor state to resume the faulted educational activity once the operating system has handled the exception. Several companies did succeed in making 68000-based Unix workstations with virtual memory that worked by using two 68000 fries running in parallel on different phased clocks. When the "leading" 68000 encountered a bad memory access, extra hardware would interrupt the "main" 68000 to preclude information technology from too encountering the bad retentiveness admission. This interrupt routine would handle the virtual memory functions and restart the "leading" 68000 in the correct state to go on properly synchronized operation when the "chief" 68000 returned from the interrupt.

These problems were fixed in the next major revision of the 68K compages, with the release of the MC68010. The Bus Error and Address Error exceptions pushed a large corporeality of internal state onto the supervisor stack in order to facilitate recovery, and the MOVE from SR instruction was fabricated privileged. A new unprivileged "MOVE from CCR" instruction was provided for use in its place by user mode software; an operating system could trap and emulate user-fashion MOVE from SR instructions if desired.

Instruction prepare details

The standard addressing modes are:

  • Annals straight
    • data register, e.g. "D0"
    • address register, eastward.k. "A6"
  • Register indirect
    • Simple address, due east.grand. (A0)
    • Accost with mail-increment, e.thousand. (A0)+
    • Accost with pre-decrement, eastward.g. -(A0)
    • Address with a xvi-fleck signed offset, e.one thousand. 16(A0)
    • Register indirect with index register & 8-bit signed offset e.g. eight(A0, D0) or 8(A0, A1)

Note that with (A0)+ and -(A0), the bodily increment or decrement value is dependent on the operand size: a byte access increments the address register by 1, a word past ii, and a long past four.

  • PC (plan counter) relative with displacement
    • Relative 16-bit signed offset, e.g. xvi(PC). This mode was very useful for position-independent code.
    • Relative with 8-scrap signed offset with index, e.g. 8(PC, D2)
  • Absolute retentivity location
    • Either a number, e.g. "$4000", or a symbolic name translated past the assembler
    • Most 68000 assemblers used the "$" symbol for hexadecimal, instead of "0x" or a trailing H.
    • At that place were sixteen and 32-fleck version of this addressing mode
  • Immediate mode
    • Data stored in the teaching, e.k. "#400"
  • Quick Immediate fashion
    • 3 fleck unsigned (or 8 bit signed with moveq) with value stored in Opcode
    • In addq and subq, 0 is the equivalent to viii
    • e.1000. moveq #0,d0 was quicker than clr.l d0 (though both made d0 equal 0)

Plus: admission to the condition register, and, in subsequently models, other special registers.

Most instructions have dot-letter suffixes, permitting operations to occur on eight-bit bytes (".b"), 16-bit words (".w"), and 32-bit longs (".fifty").

Most instructions are dyadic, that is, the performance has a source, and a destination, and the destination is changed. Notable instructions were:

  • Arithmetics: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU, DIVS, NEG (condiment negation), and CMP (a sort of comparison done by subtracting the arguments and setting the status bits, merely did not store the result)
  • Binary Coded Decimal Arithmetic: ABCD, and SBCD
  • Logic: EOR (exclusive or), AND, Non (logical non), OR (inclusive or)
  • Shifting: (logical, i.e. correct shifts put zero in the most pregnant bit) LSL, LSR, (arithmetic shifts, i.e. sign-extend the most significant bit) ASR, ASL, (Rotates through eXtend and not:) ROXL, ROXR, ROL, ROR
  • Chip test and manipulation in memory: BSET (to 1), BCLR (to 0), BCHG (invert Flake) and BTST (ready the Zero bit if tested flake is 0)
  • Multiprocessing command: TAS, test-and-gear up, performed an indivisible bus operation, permitting semaphores to be used to synchronize several processors sharing a single retentivity
  • Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return from subroutine), RTE (return from exception, i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), CHK (a conditional software exception)
  • Branch: Bcc (a branch where the "cc" specified 1 of 16 tests of the status codes in the status annals: equal, greater than, less-than, carry, and most combinations and logical inversions, available from the status register).
  • Decrement-and-branch: DBcc (where "cc" was equally for the branch instructions) which decremented a D-register and branched to a destination provided the condition was still truthful and the register had not been decremented to -1. This apply of -1 instead of 0 as the terminating value allowed the easy coding of loops which had to do nothing if the count was 0 to begin with, without the demand for an additional check earlier entering the loop. This also facilitated nesting of DBcc.

68EC000

Motorola 68EC000 controller

The 68EC000 is a low-toll version of the 68000, designed for embedded controller applications. The 68EC000 can accept either a 8-bit or xvi-bit information bus, switchable at reset. [13]

The processors are bachelor in a variety of speeds including 8 and 16 MHz configurations, producing 2,100 and 4,376 Dhrystones each. These processors have no floating signal unit and it is difficult to implement an FPU coprocessor (MC68881/2) with one considering the EC series lacks necessary coprocessor instructions.

The 68EC000 was used as a controller in many audio applications, including Ensoniq musical instruments and sound cards where information technology was role of the MIDI synthesizer. [14] On Ensoniq sound boards, the controller provided several advantages compared to competitors without a CPU on lath. The processor immune the board to be configured to perform various audio tasks, such equally MPU-401 MIDI synthesis or MT-32 emulation, without the use of a TSR plan. This improved software compatibility, lowered CPU usage, and eliminated host system memory usage.

The Motorola 68EC000 core was later used in the m68k-based DragonBall processors from Motorola/Freescale.

Information technology also was used equally a audio controller in the Sega Saturn game console, and every bit a controller for the HP JetDirect Ethernet controller boards for the mid-90s LaserJet printers.

Encounter also

  • Motorola 68000 family unit
  • Motorola 6800/6809, 8-chip
  • Freescale 68HC11, eight-chip embedded
  • x86, the Intel competitor
  • MacsBug, low-level associates/auto-level debugger
  • Zilog Z80, 8-flake

Notes

  1. ^ Motorola Literature Distribution, Phonenix, AZ (1992). M68000 Family unit Programmer's Reference Manual. [motorola]. pp. 1–1. ISBN 0-13-723289-6. http://www.freescale.com/files/archives/doc/ref_manual/M68000PRM.pdf.
  2. ^ [1]
  3. ^ [2] DTACK GROUNDED, The Journal of Uncomplicated 68000/16081 Systems Issue # 29 - March 1984 p9
  4. ^ [3] DTACK GROUNDED, The Journal of Simple 68000/16081 Systems Effect # 29 - March 1984 p9
  5. ^ [4] DTACK GROUNDED, The Journal of Unproblematic 68000/16081 Systems Issue # 29 - March 1984 p9
  6. ^ "Company Briefs", The New York Times, September 21, 1985, bachelor from TimesSelect (subscription).
  7. ^ "68HC001 obsoletes 68008.", Microprocessor Report, June 20, 1990; available from HighBeam Research (subscription).
  8. ^ "Motorola streamlines 68000 family; "EC" versions of 68000, '020, '030, and '040, plus low-end 68300 chip.", Microprocessor Written report, April 17, 1991; bachelor from HighBeam Research (subscription).
  9. ^ "Motorola reveals MC68SEC000 processor for low power embedded applications", Motorola press release, Nov 18, 1996; archived by Cyberspace Annal on March 28, 1997.
  10. ^ comp.sys.m68k Usenet posting, May 16, 1995; also see other posts in thread. The finish-of-life proclamation was in late 1994; according to standard Motorola finish-of-life practice, final orders would have been in 1995, with final shipments in 1996.
  11. ^ "Multiprotocol processor marries 68000 and RISC.", ESD: The Electronic System Design Magazine, November 1, 1989; available from AccessMyLibrary.
  12. ^ http://www.freescale.com/webapp/search/Serp.jsp?QueryText=68020
  13. ^ Boys, Robert. M68k Ofttimes Asked Questions (FAQ), comp.sys.m68k, October 19, 1994.
  14. ^ Soundscape Elite Specs. from Fax Sheet, Google Groups, Apr 25, 1995.

References

  • Motorola MC68000 Family Programmer's Reference Transmission
  • comp.sys.m68k FAQ

External links

  • Descriptions of assembler instructions
  • 68000 images and descriptions at cpu-collection.de
  • 'Chips : Of Diagnostics & Debugging' Article
  • The Vintage Mac Museum: 9inch/mono Display 68000 Simply
  • EASy68K, an open-source 68k assembler for Windows.
  • Feralcore, an open-source 68k emulator, disassembler, and debugger for Coffee.
  • Kiwi - an 68k Homebrew Computer

How To Add Two Data Registers In Motorola,

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